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Vivek Sehgal is an ASIC Digital Design, Sr Staff Engineer at Synopsys Inc, where they focus on NOC IP/SOC level verification. With extensive experience in PCIe and a strong background in IP/SOC level verification, they previously served as the PCIe PHY test suite owner. Vivek presented at PCI-SIG DevCon in 2020, discussing insights and challenges in PCIe link training verification. They hold a Bachelor of Technology in Electronics and Communications Engineering from Delhi College of Engineering, completed in 2017.