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Mahesh J. is a Senior Silicon Design Engineer at AMD, specializing in RTL Design of Security IP since 2023. They hold a Master’s degree in Computer Engineering from North Carolina State University, where they achieved a perfect GPA of 4.0. Previously, Mahesh interned at AMD, focusing on GPU performance modeling, and at Qualcomm, where they worked on CPU RTL design. Their experience also includes a role as an ASIC Engineer at NVIDIA, where they contributed to the design of clock and reset logic in Tegra SoCs. Additionally, Mahesh has served as a teaching assistant at both the International Institute of Information Technology and North Carolina State University.