Roberto Romanato is an experienced FPGA and Signal Processing Engineer currently working at Thales Alenia Space since January 2021, focusing on the architectural design and FPGA implementation of onboard processors for Sicral 3 satellites and contributing to the ESPRIT project for the Lunar Gateway. Prior to this role, Roberto spent over 13 years at Airbus Italia S.p.A., where responsibilities included digital circuit design and leading the Navigation Signal Generation Unit design for the Galileo Payload TestBed. Early career experience includes a position at Universit degli Studi di Roma 'La Sapienza' involving synthesis and place-and-route for digital signal processors. Roberto holds a Masters and Bachelors degree in Electronic Engineering from Sapienza Universit di Roma, as well as a High School Diploma in Computer Science from ITIS Guglielmo Marconi.
Location
Rome, Italy
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