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Stan Sokorac

Processor Engineering

Keith Witek

Chief Operating Officer and Board Member

Andy Wall

Director, Global Trade Compliance

Joshua Bell

Sr. Principal, Physical Design Flows

Dan Bailey

Senior Fellow, Lead Of Physical Engineering

Nitin Mohan

Sr. Principal Engineer, Physical Design

Andy Halliday

Senior Principal Engineer

Brian Chen

Staff CPU Engineer

Dongyuan Zhan

Principal Engineer

Melanie Crain

Director, AI/ML Product Management

Bob Grim

Vice President Of Strategy And Corporate Communications

Hayley Slotboom

Senior Communications Specialist

Thaddeus Fortenberry

Sr. Principal Engineer, Large Scale ML Computer Architect

Anurag Atmakuri

Sr. Staff Physical Design Engineer

Jason Chiang

Director, Field And Application Engineering

Suresh Hariharan

Fellow

Paul Keller

Fellow

Ken Dockser

Senior Principal Architect

Nicholas Smith

Senior Principal Software Engineer

Nicole Lusignan

Director Of Revenue Operations

Parth Modi

Senior Manager, Global Supply Management

Sarvani Kunapareddy

Sr. Physical design engineer

Matt Craighead

Principal Engineer, AI HW

Robert Sweeney

Sr. Principal, Physical Design Methodologies

Manie F Davis

Director Business Enablement, Customer Team

Daniel DeGrasse

Senior Firmware Engineer

Matt Day

Senior Principal Engineer

Andy Gross

Principal Engineer

Teresa Hinojosa-Cardwell

Principal TPM, Product Development Process Manager

Ken Gildersleeve

Staff Engineer, RISC-V

Colby Renfro

Staff Engineer Design Verification

Arik Yaacob

Principal Software Engineer

Vishwasree Routh

CPU Physical Design Intern

Mike Gupta

Senior Staff Technical Program Manager

David Rea

Staff Design Engineer

Simon Wu

Staff Product Manager - RISC-V CPU IP

Dakota Luther

Communications Specialist

Pratyush Jain

CPU Engineer

Bill Greene

Head of IP Engineering

Anantha Thummalapalli

Physical Design Engineer

Michael Thome

IT Administrator

Nikhil Soraba

Senior Staff Software Engineer

Daniel Kruczek

Technical Program Manager

Siddharth Sundaram

Software Engineer

John Mappes

Senior Power Integrity Engineer

Yash Salunke

IP Packaging & Verification Intern

David Cho

Principal Engineer, Architecture