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Peter Rosefield is a highly experienced engineer with a robust background in analog and mixed signal circuit design. Peter began a career at Bell Northern Research, simulating various circuits before developing skills at companies such as AECL and ATI Technologies in PCB design and custom silicon layout. At AMD, Peter served as a Senior Engineer focused on analog circuit design and later built and led the "I/O Functional Design" team as a Sr. Manager. Currently, Peter works at Synopsys Inc as a Sr Staff Analog and Mixed Signal Circuit Design Engineer, with previous experience as a Field Application Engineer at Peraso Technologies, providing support for advanced wireless products. Peter holds a Bachelor of Applied Science in Electrical and Electronics Engineering from the University of Waterloo.