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Pavan Chopade is a Staff Engineer specializing in ASIC Physical Design at Synopsys Inc. With a strong background in physical design steps from RTL to GDSII flow for technology nodes ranging from 130nm to 3nm, Pavan has demonstrated expertise in both block and top-level design implementations. Previously, they held positions at HCL Technologies and L&T Technology Services Limited, where they contributed to various physical design projects. Pavan began their career as a VLSI Trainee at LinkedLoops Technologies, where they developed and integrated firmware for embedded systems. They completed a Bachelor of Technology in Electronics Engineering from Walchand College of Engineering, achieving consistent performance in academics and extracurricular activities.