Bhavna Agarwal is a skilled RTL Design Engineer with extensive experience in the electronics and semiconductor industries. They have worked at Intel Corporation from 2019 to 2023, focusing on various projects including error handling IP and power management design, while also gaining expertise through roles at Sankalp Semiconductor and Maven Silicon. Currently, Bhavna serves as a Senior Lead Design Engineer at Qualcomm, contributing to Qlink IP design. They earned a Bachelor of Technology in Electrical and Electronics Engineering from Veer Surendra Sai University of Technology, graduating in 2017.
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Bengaluru, India
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