ÂÜÀòÂÒÂ×

Mudhassar Ibrahim Sajath is an ASIC Verification Engineer at Palo Alto Networks and a recent graduate from The University of Texas at Dallas, where they earned a Master’s Degree in Electrical and Electronics Engineering. Currently, they work as an MTS Design Verification Engineer at AMD and previously served as a Design Verification Engineer at Intel Corporation. Mudhassar's technical expertise includes hardware description languages such as Verilog, System Verilog, and VHDL, as well as various design and simulation tools. They also have a background in programming with languages including PERL, Python, and SQL, and have experience as a Program Analyst at Cognizant India Pvt. Ltd.