ÂÜÀòÂÒÂ×

Naveen Kumar Kolavanahalli Ramach is a Senior FPGA Modeling Engineer at Microsoft, where they currently apply their expertise in digital design. They previously served in various roles at Intel Corporation, including FPGA RTL Design Engineer and Logic Design Engineer, from 2016 to 2023. Naveen began their career as a Quality Assurance Engineer at Cognizant Technology Solutions and holds a Bachelor of Engineering in Electrical, Electronics and Communications Engineering from Sir M Visvesvaraya Institute of Technology, as well as a Master’s Degree in Digital IC Design from Portland State University.