Varun Pavagada Matha is an experienced engineering professional specializing in semiconductor design and validation. Currently serving as a Staff Design Validation Product Engineer at Micron Technology since February 2024, Varun previously held the role of Physical Design Integration Engineer at Intel Corporation, where contributions included layout development for advanced 3D ICs. At Micron Technology from February 2018 to February 2024, Varun advanced from Senior Layout Engineer to IC Layout Designer, executing custom layouts for DRAM products and collaborating with various teams on memory device specifications. Earlier experience includes a position as IC Layout Design & PDK Support Engineer at Western Semiconductor, focusing on layout planning and execution for both analog and digital designs. Varun holds a Master's degree in Electrical and Electronics Engineering from the Rochester Institute of Technology and a Bachelor of Engineering in Electrical, Electronics and Communications Engineering from BNM Institute of Technology.
This person is not in any teams
This person is not in any offices