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Kang Zhang is an experienced engineering professional with a solid background in logic design and memory subsystem architecture. Beginning a career in logic design at Shanghai Jiao Tong University, where a B.S. in Electrical Engineering was earned, and advancing to the University of Michigan for an M.S. in VLSI, Kang Zhang held several positions at Marvell Semiconductor, including Staff Logic Design Engineer focused on Final Level Cache (DRAM Cache Controller), and also served as a Summer Intern in the CPU group. A transition to FLC Technology Group as a Staff Logic Design Engineer was followed by a current position as a Digital Design Engineer at Meta, starting in March 2019.