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Michael Raj Varuvel has over two decades of experience in ASIC physical design, currently serving as ASIC Physical Design Manager at MaxLinear since April 2011, where responsibilities include leading the physical design process from Netlist to GDS2 and JDV. Previously held roles encompass Senior Principal ASIC PnR Engineer at MaxLinear, with significant involvement in 40, 28, 16, 14, and 5nm chip implementations, and Physical Design Technical Lead at KPIT, where more than seven multi-million gate designs were completed. Earlier experience includes positions at Arm, focusing on core implementation and layout, and at Spike Technologies, handling cell layout design and library generation. Michael Raj Varuvel earned a Master of Science in VLSI Design from Ramaiyah School of Advanced Studies, Coventry University UK, between 2006 and 2008.