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Francisco Alderete is a Hardware Design Verification Engineer with extensive experience in RTL verification and IP verification, currently at Intel Corporation since July 2022. Responsibilities include AI-assisted testbench generation, pre-silicon verification, and Ethernet subsystem verification, utilizing UVM and OVM methodologies. Prior to Intel, Francisco worked at Raytheon from April 2019 to July 2022, focusing on ASIC digital products, where tasks included chip RTL verification, gate-level verification, and synthesis debugging. Experience also includes role as an Electrical Engineer at Honeywell FM&T, emphasizing process engineering and teamwork, and a Product Development Engineer Intern position at Intel, where contributions were made in the Internet of Things Group. Francisco holds a Bachelor's Degree in Electrical and Electronics Engineering from The University of Texas at Dallas.