Devesh Kumar is a Principal Design Engineer at Cadence Design Systems, specializing in DDR Memory Controller IP Verification since November 2022. Prior to this role, Devesh served as a Technical Lead at STMicroelectronics from March 2020 to November 2022, focusing on IP level, subsystem level, and SOC verification. Devesh also held the position of Senior Engineer at Altran from May 2018 to March 2020, where responsibilities included IP level and subsystem level verification. Devesh began the career as a Senior Research and Development Engineer at Synopsys from July 2011 to May 2018, concentrating on the development and verification of VIP. Devesh holds a Bachelor of Technology (B.Tech.) degree in Electronics and Communications Engineering from Bharati Vidyapeeth, obtained in 2011.
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