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Rajesh Balakrishnan is a Design Verification specialist with extensive experience in constrained random functional verification within the front-end ASIC flow. They have worked as a verification engineer for peripheral modules using System Verilog and OVM at NEC Electronics and have held positions at companies such as IBM, where they focused on PCIe link training verification, and Cisco Systems in ASIC verification. Currently, Rajesh serves as a Principal Verification Engineer at Arm, leveraging their knowledge in System Verilog, functional coverage concepts, and PCIe. They earned a B.Tech in Electronics and Communication from LBS College of Engineering.