Mahesh Palaka is currently an FPGA IP Software Development Engineer at Altera (Intel), where they focus on functional verification by utilizing functional coverage and developing reusable testbench coding for Ethernet IPs. Previously, Mahesh gained hands-on experience in digital design and verification as part of their role in advanced VLSI design and verification. They are pursuing a Bachelor of Technology in Electronics and Communication Engineering at Aditya University, demonstrating a strong commitment to continuous learning and excellence in the field of design and verification.
This person is not in the org chart
This person is not in any offices