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Rohan Sikka is a seasoned engineering professional with expertise in front-end implementation and silicon design. Currently serving as a Member of Technical Staff in the AECG team at AMD since February 2021, Rohan Sikka has successfully developed SDC constraints, performed design synthesis, and enhanced timing quality for complex hierarchical designs. Prior to AMD, Rohan Sikka worked at Intel Corporation from February 2017 to February 2021 as a SoC Design Engineer, where responsibilities included developing Lint and synthesis flows, performing netlist equivalence checking, and generating regression flows. Rohan Sikka holds a Master of Science in Electrical Engineering from Stony Brook University and a Bachelor of Engineering in Telecommunications Engineering from Ramaiah Institute of Technology.